The present invention relates generally to the art of semiconductor fabrication. More particularly, the present invention relates to an improved isolation technique for CMOS memory cells. Even more particularly, the invention relates to the use of a thick oxide field shield CMOS fabrication process.
One of the most challenging problems in the present art of semiconductor fabrication is that of providing increased memory cell capacity on a single chip. Typically, as dynamic RAM sizes increase from 64K to 256K and on up to 1 megabyte levels, it becomes increasingly necessary to reduce the space between the memory cells so that the overall chip size remains reasonable. However, as the space between the memory cells is decreased, it becomes necessary to preserve the isolation characteristics of that intervening space. If this is not done, the accuracy of the memory chip becomes unacceptable because of leakage from one memory cell to another.
Similarly, the capacitance of each memory cell must be held relatively constant even as the number of memory cells per chip increases. It will be appreciated that this is essentially inconsistent with accepted notions of chip area scaling. The capacitance of the memory cell itself is important because of the alpha radiation which all chips are subjected to in our atmosphere. If the overall cell capacitance becomes too small, the memory cell will become readily neutralized by the impact of the alpha particles within the semiconductor cell structure.
Traditionally, N-channel dynamic RAM processes provide cell isolation using a local oxidation method which causes the space between cells to grow at every process step. Thus, the resulting space between cells is normally far greater that the minimum required to achieve acceptable isolation of memory cells. This result is inconsistant with the goal of adding additional memory cells to the same chip while at the same time maintaining a relatively constant overall size. Thus, it is desirable to use a new isolation method for separating the memory cells to be contained on one chip without unduly increasing the size of that chip.
Two conventional methods are known for providing the isolation between adjacent memory cells. The first of these is illustrated generally in FIG. 1A. Two adjacent transistors 2 and 4 are shown having a large growth of field oxide 5 between them. This oxide takes advantage of the fact that an isolation transistor 9 is naturally formed by the structure of the chip between each active transistor or memory cell. The field oxide serves to create a gate with a relatively high threshold voltage. Because this threshold voltage is normally higher the transient stimuli traditionally found on a memory chip, the transistor formed between the adjacent cells is always "off". This effectively isolates one memory cell from the next. However, because of the use of this field oxide 5, the size of the memory cells is inordinately limited when the chip is processed through the number of steps necessary to create a very large scale memory chip. As mentioned above, this field oxide 5 grows with each step and creates a resulting space between the cells which is far greater than the minimum space required to achieve acceptable isolation.
A second known method for achieving isolation between adjacent memory cells is illustrated generally in the naturally formed transistor 6 between adjacent memory cells 3 and 7. In this scheme the gate 8 of the intervening transistor is developed on a polysilicon base which is tied to ground. As in the scheme above, this keeps the intervening transistor in a perpetual "off" state, thus isolating the two memory cells.
However, while this method does not cause the space between cells to grow to an inordinate amount in the number of steps necessary to fabricate a semiconductor memory chip, it fails to solve the problem of reduced capacitance in the memory cells as they are scaled down in size. Specifically, the thin oxide used in this scheme allows only the most basic of dielectric materials to be used. The use of an enhanced dielectric such as silicon nitride would create an unstable isolation transistor in the resulting memory structure due to the charge trapped at the boundary between the thin oxide and the nitride.
The present invention therefore concerns the overall process of making larger memory devices and reconciling the space requirements of each memory cell with physical/electrical requirements.
Thus, a principal object of the present invention is to provide a method for fabrication of a semiconductor memory structure having a cell size adequate for capacitance purposes while at the same time permitting a one megabit memory without excessive space. It will be appreciated that a related object of the present invention is to provide for maximizing the number of memory cells which may be contained on a given chip.
A further object of the present invention is to allow for a greater capacitance in each memory cell without increasing the space necessary for that cell.
Still a further object of the present invention is to provide a CMOS fabrication process which will allow for the use of thick oxide field-shield isolation in peripheral circuits as well as in the memory circuit itself.
It will be appreciated then that an even further object of the present invention is to minimize the number of steps of growing, masking, and etching needed to fabricate a semiconductor memory cell device.